1. Field of the Invention
The present invention relates to a thin film transistor (TFT) array substrate and a process for manufacturing the same. More specifically, the present invention relates to a TFT array substrate for a self-aligned in-plane switching (IPS) liquid crystal display.
2. Description of the Related Art
The cathode ray tube (CRT), having superior display quality and economic effect, has been widely used as a display device. However, there are some issues with respect to the CRT device such as space utility and power consumption. As the demand for a display device having light-weight and compactness increases, a thin film transistor liquid crystal display (TFT-LCD) device to meet the current requirements has been increasingly used. However, the LDC device usually has a narrow range of viewing angle and a high price. Multi-processing of a large substrate has been proposed to produce a LCD device sold at a reduced price. In order to overcome the limitation of the view angle range, many solutions have been proposed, such as pixel division, optical film phase complement, and diffusion plate pixel projection.
FIG. 1A is a top view of a TFT array substrate for a conventional IPS liquid crystal display device. FIG. 1B is a schematic cross sectional view taken along line IIxe2x80x94II of FIG. 1. It is a characteristic of the IPS liquid crystal display device that the liquid crystal molecules rotate only in the horizontal direction in the same plane. A TFT array substrate mainly consists of a transparent substrate having a plurality of TFTs 102 in array. Each of the TFTs 102 corresponds to a pixel region 104 which has a plurality of metal common electrodes 106 and a plurality of metal pixel electrodes 108. The metal common electrode 106 is located under the metal pixel electrode 108 and an insulating layer 107 is interposed there between. A source/drain region 110 of the TFT 102 is electrically connected to a signal line 114 and a metal pixel electrode 108. A protection layer 116 is further formed over the transparent substrate 100 to cover the TFT 102 and the pixel region 104. By action of a horizontal electric field between the metal pixel electrode 108 and the metal common electrode 106, the liquid crystal molecules rotate in a same plane in a direction parallel to the substrate to display, thereby reducing the dependency on view angle.
With reference to FIG. 2A, since there is a horizontal electric field between the metal pixel electrode 108 and the metal common electrode 106 in the conventional IPS liquid crystal display device, broader range of view angle is provided. However, the liquid crystal molecules above the metal pixel electrode 108 or the metal common electrode 106 can not display due to the horizontal electric field, causing a low aperture issue.
With reference to FIG. 2B, in order to overcome the low-aperture problem of the conventional IPS liquid crystal display, a FFS liquid crystal display device has been proposed. In the FFS liquid crystal display device, a transparent pixel electrode 108b is formed on a transparent common electrode 106b with a distance smaller than a width of an electrode and a cell gap of a display, so that the horizontal electric field is distributed uniformly between and above the electrodes 106b and 108b and the aperture of the IPS liquid crystal display device is thus increased. However, the FFS liquid crystal display device has some drawbacks, for example, electrode gaps defined by different masks are difficult to control. Furthermore, after the underlay transparent common electrode 106b is formed, a mask and a deposition process are required to pattern the transparent pixel electrode 108b. Alignment of the transparent electrodes 108b and 106b is critical to the manufacturing process. If misalignment occurs, then the electric field can not be distributed uniformly and the display quality can be adversely effected. Further, a big liquid crystal display is formed of small liquid crystal display cells. Shot mura issue tends to occur in assembly of liquid crystal cells made by a conventional process, especially an exposure process using a stepper.
In one aspect of the present invention, a TFT array substrate and a process for manufacturing the same are provided. The TFT array substrate of the present invention has advantageously high aperture and transparent electrodes that disconnect but overlap each other. The transparent electrodes in the TFT array substrate can be self-aligned so that misalignment of electrodes in the prior art can be avoided.
In order to achieve the above and other objects of the present invention, a TFT array substrate and a process for manufacturing the same are provided. A plurality of TFTs in array are formed on a transparent substrate by a conventional process for producing a TFT. During the TFT process, a first metal is used to form a scan line, a gate and a common line. A gate insulating layer and a protection layer are sequentially formed in a pixel region of the transparent substrate. By selecting the material type of an etchant, the gate insulating layer and the protection layer, an etching rate of the gate insulating layer can be controlled to be larger than that of the protection layer, so that a plurality of openings are formed in the gate insulating layer and the protection layer. The opening in the gate insulating layer has an undercut profile. Then, a transparent conductive layer is formed over the substrate. Since the opening has an undercut profile, the transparent conductive layer separates into two parts at the edge of the opening. One of the two parts separated is located in a bottom of the opening and the other is on the protection layer, such that two parts of the transparent conductive layer disconnect and no junction there between occurs. The part of the transparent conductive layer in the bottom of the opening is referred to as a transparent pixel electrode. The part of the transparent conductive layer on the protection layer is connected to a common metal line to form a transparent common electrode.
Another TFT array substrate and a process for manufacturing the same are also provided. A plurality of TFTs are formed in array on the substrate by a conventional process. The gate insulating layer can be a multi-layered structure, such as a two-layered structure having a first insulating layer and a second insulating layer. In the case of the two-layered structure recited above, the first insulation and the second insulating layer overlie a pixel region of the substrate. By selecting the material type of an etchant, the gate insulating layer and the protection layer, an etching rate of the first insulating layer can be controlled to be larger than that of the second insulating layer, so that a plurality of openings are formed in the first insulating layer and the second insulating layer. The opening in the first insulating layer has an undercut profile. Then, a transparent conductive layer is formed over the substrate. Since the opening has an undercut profile, the transparent conductive layer separates into two parts at the edge of the opening. One of the two parts separated is located in a bottom of the opening and the other is on the second insulating layer, such that two parts of the transparent conductive layer disconnect and no junction there between occurs. The part of the transparent conductive layer in the bottom of the opening is referred to as a transparent pixel electrode. The part of the transparent conductive layer on the second insulating layer is connected to a common metal line to form a transparent common electrode.